Major State Generator
This is the circuitry that keeps track of the major state. There is one
D flip-flop for each state, clocked by CLOCKP, with logic connected to
its D input that computes whether it should be the next state entered.
Some states can also be entered in response to pulses from the front
panel buttons; in these cases, the flip-flops are set or cleared
directly using their S* and R* inputs.
The Load Address, Deposit and Examine states are only ever entered via
front panel
control pulses, so simple RS latches are used for these instead of D
flip-flops.
Most of the input signals to this circuit come from the Front Panel
Control and Master Clock circuits. The MEMREF and INDIRECT signals are
derived from the data being read from memory during a fetch cycle, and
indicate a memory reference
instruction and indirect addressing respectively.
The PAUSE* signal can be asserted by an I/O device to keep the machine
in the Execute state for additional clock cycles. It is not used by the
basic machine.
